D flip-flop

D flip-flop
D flip-flop symbol



The Q output always takes on the state of the D input at the moment of a rising clock edge, and never at any other time. ^[4] It is called the D flip-flop for this reason, since the output takes the value of the D input or Data input, and Delays it by one clock count. The D flip-flop can be interpreted as a primitive memory cell, zero-order hold, or delay line.
Truth table:

Clock	D	Q	Qprev
Rising edge	0	0	X
Rising edge	1	1	X
Non-Rising	X	constant

('X' denotes a Don't care condition, meaning the signal is irrelevant)
These flip flops are very useful, as they form the basis for shift registers, which are an essential part of many electronic devices. The advantage of the D flip-flop over the D-type latch is that it "captures" the signal at the moment the clock goes high, and subsequent changes of the data line do not influence Q until the next rising clock edge. An exception is that some flip-flops have a 'reset' signal input, which will reset Q (to zero), and may be either asynchronous or synchronous with the clock.
3-bit shift register




The above circuit shifts the contents of the register to the right, one bit position on each active transition of the clock. The input X being shifted into the leftmost bit position.